In a computer system having more than one memory storage facility, a special data integrity challenge can occur. Any computer system having both a main-memory structure and cache-memory(s) is in such a situation (e.g. see System I in FIG. 1, having Main Memory linked by system bus means to a number of Processors, 1,2, . . . N, each with an associated Cache Memory). The potential problem that should be faced is that of maintaining "data coherency," i.e., assuring that all copies of information (data) are identical for a given specific address (in all memory facilities - - - a "data integrity" problem.
If computer processors only read data from the memories, this problem would never occur, but, then, little productive work would take place either. Real processors must also modify the values of data that is stored in the system's memories. This is usually referred to as writing memory, or as doing an "overwrite" operation. Some systems provide for several types of write operations. No matter what varieties of write operations are used, the central problem of data coherency arises any time data in one of several memory facilities has been modified.
Most computer systems with cache memories maintain data integrity using an "Invalidation" scheme. This technique requires each cache-memory module to monitor (or spy-upon) the memory operations of all other processors in the system. When any memory "data write" operation is detected, then each of the cache-memories must plan for a potential invalidation operation within its own cache memory. Invalidation operation entails checking the contents of (its own) cache memory for the specific address of the write operation that was detected. If a local cache-memory module discovers that it indeed does contain this (same) address, it must then mark this address as no longer valid, since some other processor is overwriting its previous value.
This invalidation process, itself, presents a problem for the cache memory module and its associated processor, since it uses of cache memory resources. These resources are, of course, present to assist the processor in its work, but the invalidation process may make them "busy" and so hinder the processor from getting its regular work done.
It would be desirable therefore to remember the information necessary for a specific invalidation and execute the process at the least inconvenient time - - - such is an object hereof.
A second motivation for some sort of remembering device for invalidation data is that the "spying," or monitoring of bus activity, may involve numerous write conditions, and doing so very quickly lest one delay other processors in the system. Therefore, each spy, or cache, must remember all the possible invalidation information for execution at some later time. This we also propose here.
Such a novel "remembering mechanism," is described here - - - and, for the sake of this discussion, it is called an "INVALIDATION QUEUE" (IQ). The IQ queue structure must take-in, and hold, all pertinent information regarding all memory write operations in the system. It must then provide for the convenient unloading of this information for the invalidation process at the discretion of the local cache-memory module.
This disclosure presents such an INVALIDATION QUEUE structure; along with several special related features to greater facilitate the efficient handling of invalidation information at the least cost in overall performance of the computer system.
Thus, an object hereof is to address at least some of the foregoing problems and to provide at least some of the mentioned, and other, advantages.